The present invention relates to a semiconductor memory device, and particularly, to a DRAM (Dynamic Random Access Memory) of a clock synchronous type having an Overlaid DQ structure and pre-charging of data lines of the DRAM.
This application is based on Japanese Patent Application No. 9-37630, filed on Feb. 21, 1997, the contents of which is cited herein by reference.
FIG. 1 explains a conventional semiconductor memory device and is a block diagram showing a schematic structure of a clock synchronous type 4M-bit DRAM having an overlaid DQ structure. The DRAM comprises a memory cell array 11, a row address buffer 12, a row address buffer controller 13, a row pre-decoder 20, a circuit block 21, a DQ buffer 22, a data I/O buffer 23, a DQ pre-charge/equalize controller 24, and a DQ buffer controller 25.
The memory cell array 11 of 4M-bit consists of two 2M-bit arrays 11A and 11B, and the 2M-bit arrays 11A and 11B respectively consist of eight 256K-bit cell array blocks 11A-0 to 11A-7 and eight 256K-bit cell array blocks 11B-0 to 11B-7. Each of the cell array blocks 11A-0 to 11A-7 and 11B-0 to 11B-7 is constructed in a structure of 256 rows.times.1K columns in which dynamic type memory cells are arranged in a matrix consisting of rows and columns. The row controller 13 receives a /RAS signal and controls the row address buffer 12. The sign "/" of the /RAS signal means this signal is an inverted or a bar of a RAS signal. Hereinafter, in the present specification, "/" is used to indicate an inverted signal. When the /RAS signal is at a low level, the row address buffer 12 latches a row address signals AR0 to AR10 in synchronization with a clock signal CLK, under control of the row controller 13, and generates interpolation signals X0 to X10 and /X0 to /X10. The interpolation signals X0 to X10 and /X0 to /X10 are supplied to the row pre-decoder 14 and pre-decoded. Thereafter, the interpolation signals are supplied to the row decoder 15 provided between the 2M-bit arrays 11A and 11B and are decoded. Selection and activation are made with respect to sixteen 256K blocks 11A-0 to 11A-7 and 11B-0 to 11B-7, with use of interpolation signals X8 to X10 and /X8 to /X10 generated from upper three bits of 11 bits of the row address signals AR0 to AR10. Two blocks which sandwich the row decoder 15 are simultaneously activated (as shown in FIG. 1 in which block 11A-7 and 11B-7 marked with oblique lines are activated). Rows of memory cells are selected in the blocks selected with use of interpolation signals X0 to X7 and /X0 to /X7 generated from the other remaining 8 bits of the row address signals.
The column address buffer 16 latches a column address signal AC0 to AC2 of 3 bits in synchronization with a clock signal CLK when the signal /CAS goes to a low level under control by the /CAS buffer 18. The column address buffer 16 performs a flip-flop operation (waveforms of which will be described later) synchronized with the clock signal CLK. The column address buffer 16 converts the column address signals AC0 to AC2 into interpolation signals Y0F to Y2F and /Y0F to /Y2F. The interpolation signals Y0F to Y2F and /Y0F to /Y2F are supplied to the flip-flop 19 and are converted into Y0S to Y2S and /Y0S to /Y2S. In this step, eight selection signals (/X8.multidot./X9.multidot./X10, X8.multidot.X9.multidot.X10, . . . , and X8.multidot.X9.multidot.X10 which are abbreviated and indicated as X8.multidot.X9.multidot.X10 in the figure) of cell array blocks generated by the row pre-decoder 14 are also converted into signals X8S.multidot.X9S.multidot.X10S by the flip-flop 19. Those column address signals are supplied to the column pre-decoder 20 and column switch selection signals CSW0 to CSW3 are generated. The column switch signals CSW0 to CSW3 are generated by obtaining a logical product of upper two bits of Y1S, /Y1S, Y2S, and /Y2S and a signal X8S.multidot.X9S.multidot.X10S, as expressed in the following logic.
CSW0=/Y1S.multidot./Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW1=Y1S.multidot./Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW2=/Y1S.multidot.Y2S.multidot.X8S.multidot.X9S.multidot.X10S PA1 CSW3=Y1S.multidot.Y2S.multidot.X8S.multidot.X9S.multidot.X10S
One of the column switch signals CSW0 to CSW3 corresponding to a selected cell array block is activated by the above logical calculation.
In addition, interpolation signals Y0S and /Y0S output from the column pre-decoder 20 are supplied to a circuit block 21. The circuit block 21 consists of first and second circuit blocks 21A and 21B respectively corresponding to 2M-bit arrays 11A and 11B, and each of the first and second circuit blocks 21A and 21B is provided with a DQ multiplexer, a DQ pre-charger a DQ equalizer, and the like. Likewise, a DQ buffer 22 consists of first and second buffer sections 22A and 22B respectively corresponding to the 2M-bit arrays 11A and 11B, and outputs of the buffer sections 22A and 22B are supplied to the data I/O buffer 23 respectively through RWD busses 26A and 26B each consisting of 128 lines (i.e. total 256 lines). The data I/O buffer 23 is supplied with clock signal CLK and an output signal from a /WE buffer 17, and controls inputs/outputs of data.
The /WE buffer 17 is controlled by an output signal from the /CAS buffer 18, and latches a /WE signal. A DQ pre-charge/equalize controller 24 receives a clock signal CLK, /CAS signal, and an output signal from the /WE buffer 17 and generates a pre-charge signal /PRCH. The DQ pre-charge/equalize controller 24 uses the pre-charge signal /PRCH to control the first and second circuit blocks 21A and 21B, so that pre-charging and equalizing of DQ lines are controlled. The DQ buffer controller 25 is supplied with a clock signal CLK described above and an output signal from the /WE buffer 17, and controls the first and second buffer sections 22A and 22B of the DQ buffer 22.
256 pairs of DQ lines are provided on the 2M-bit cell arrays 1A and 11B and are connected to the DQ buffers 22A and 22B through the DQ multiplexer, the DQ pre-charger, and the DQ equalizer. In this respect, FIG. 2 shows more details. 1K columns (or a pair of bit lines) of each of the blocks 11A-0 to 11A-7 and 11B-0 to 11B-7 are connected with 1024 sense amplifiers (S/A) 27-0 to 27-1023. Outputs of the sense amplifiers are supplied to multiplexers (4:1 MUX) 28-0 to 28-255, in units of four outputs. Output ends of the multiplexers 28-0 to 28-255 are respectively connected to 256 pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255. By four column switch selection signals CSW0 to CSW3 output from the column decoder 20, one is selected from output signals of four sense amplifier, supplied to each of the multiplexers 28-0 to 28-255, and is output to pairs of DQ lines 29-0 and /29-0 to 29-255 to /29-255. The pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255 are connected with PMOS transistors 30-0 to 30-255 which serve as DQ equalizers, and with PMOS transistors 31-0 to 31-255 and 32-0 to 32-255 which serve as DQ pre-chargers. The current paths of the PMOS transistors 30-0 to 30-255 is connected between the DQ lines 29-0 to 29-255 and a power source Vcc. The current paths of the PMOS transistors 31-0 to 31-255 are connected between the DQ lines /29-0 to /29-255 and the power source Vcc. The gates of the PMOS transistors 30-0 to 30-255, 31-0 to 31-255, and 32-0 to 32-255 are supplied with a pre-charge signal /PRCH output from the DQ pre-charge/equalize controller 24 to perform ON/OFF control.
The 256 pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255 are connected to 128 DQ multiplexers (2:1 MUS) 33-0 to 33-127, in units each consisting of two pair of DQ lines. Each of the DQ multiplexers 33-0 to 33-12 selects one pair of two pairs of DQ lines connected thereto, in accordance with interpolation signals Y0S and /Y0S (or the lowermost bit of the column address) output from the column pre-decoder 20. Specifically, when the signal /Y0S is at a high level, pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . ., and 29-255, and /29-255 are selected, and data on these DQ lines is supplied to the DQ buffers 22-0 to 22-127, so that read data is amplified. Output signals of the DQ buffers 22-0 to 22-127 are respectively supplied to RWD busses 26-0 to 26-127.
In the structure as described above, 1K lines of columns corresponding to the 2M cell arrays 11A and 11B are multiplexed at a ratio of 4:1 by the column switch selection signals CSW0 to CSW3, and are connected to the 256 pairs of DQ lines. In this state, the column switch selection signals CSW0 to CSW3 are common to the 256 pairs. Specifically, when one of the column switch selections signals CSW0 to CSW3 is selected, e.g., when the signal CSW0 is selected, 256 sense amplifiers 27-0, 27-4, 27-8, . . . , and 27-1021 are simultaneously connected to the pairs of DQ-lines 29-0 and /29-0, 29-1 and /29-1, . . . , and 29-255 and /29-255, and data held by the sense amplifiers is read out onto the DQ lines.
FIG. 3 is a block diagram extracting and more specifically showing a circuit section relating to bit lines, sense amplifiers and pairs of DQ lines shown in the block diagram of FIG. 2. 1K pieces of sense amplifiers 27 are divided into groups each consisting of four sense amplifiers and arranged at both ends of each of 256K blocks. Each sense amplifier 27 is connected with a pair of bit lines BL and /BL. The pairs of bit lines BL and /BL are arranged such that bit lines of the sense amplifiers in one side are inserted between bit lines of the other sense amplifiers in the opposite side. Four sense amplifiers 27 of each group are connected to a pair of DQ lines 29 and /29, through current paths of NMOS transistors 34-0 to 34-7 which serve as a multiplexer 28, respectively. The gates of the NMOS transistors 34-0 to 34-7 are supplied with column switch selection signals CSW0 to CSW3, output data of the sense amplifier 27 corresponding to that one of the column switch selection signals which is of a high level is read out onto the pair of DQ lines 29 and /29.
The pair of DQ lines 29 and /29 is used in common by eight cell array blocks and is arranged in a direction parallel to the bit lines BL and /BL (i.e., in an overlaid DQ structure). A DRAM having this overlaid DQ structure allows a number of pairs DQ lines to be provided in a small chip area, and is therefore used for a logic mixture DRAM having a large number of data inputs and outputs.
FIG. 4 is a timing chart for explaining operation of the circuit shown in FIGS. 1 to 3. Next, explanation of the operation will be made mainly with respect to pre-charge and equalize operation. Here, operation of column access will be made, supposing that a low address signal has been taken in with the /RAS signal kept at a low level, a word line has been selected, and latch operation of a selected row has been carried out.
When the /CAS signal goes to a low level, column address signals AC0 to AC2 are taken in by the column address buffer 16 by control of the /CAS buffer 18, and column addresses CA0, CA1, and CA2 are sequentially generated in clock cycles 0 to 2, respectively. A column access signal path from the column address buffer 16 to a data output is divided into three pipe line stages, e.g., the column address buffer 16 which performs flip-flop operation, a flip-flop 19 in the stage before the column pre-decoder 20, and a data I/O buffer 23 which also performs flip-operation. The route through which signals Y0F to F2F are transmitted from the column address buffer 16 to the flip-flop 19 is the first stage PS1. The route through which signals CSW0 to CSW3 and signals Y0S and /Y0S from the flip-flop 19 are activated and data of selected columns are latched by the data I/O buffer 23 through the pair of DQ lines 29 and /29, the DQ multiplexer 33, and the DQ buffer 22 is the pipe line second stage PS2. The last pipe line third stage PS3 corresponds to data outputting from the data I/O buffer 23.
In putted column addresses CA0, CA1, CA2, . . . are transmitted through the pipe line stages PS1, PS2, and PS3 in clock cycles 0, 1, 2, . . . , respectively. Specifically, signals /Y0F, /Y1F, and /Y2F are activated in the 0th clock cycle, and signals /Y0S, /Y1S, and /Y2S, and CSW0 are activated in the next first clock cycle. When the signal CSW0 is thereby turned to a high level, data of sense amplifiers 27-0, 27-4, . . . , 27-1021 shown I FIG. 2 is read through pairs of DQ lines 29-0 and /29-0 to 29-255 and /29-255. Since the signal /Y0S is now at a high level, data of the pairs of DQ lines 29-0 and /29-0, 29-2 and /29-2, . . . , 29-254 and /29-254 among 256 pairs of DQ lines is supplied to the DQ buffers 22-0 to 22-127 through the multiplexers 33-0 to 33-127 and is amplified. In this state, data of the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255 does not passes through the multiplexers 33-0 to 3-127, and therefore is not read onto the DQ buffers 22-0 to 22-127.
Next, the column address CA1 input before the first clock cycle activates the signals Y0F, /Y1F, and /Y2F in the first clock cycle, and further, activates the signals Y0S, /Y1S, /Y2S, and CSW0 in the second clock cycle. Since the signals /Y1S, /Y2S, and CSW0 have already been activated in the first clock cycle, data to be read (D1 in FIG. 4) has already been output to the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255.
However, in a conventional clock synchronous DRAM as described above, since the pairs of DQ lines are pre-charged and equalized in every clock cycle, and data read out onto the pairs of DQ lines 29-1 and /29-1, 29-3 and /29-3, . . . , 29-255 and /29-255 is broken by the pre-charging and equalizing operation and is read out again onto these DQ lines in the second clock cycle. Such wasteful pre-charging and equalizing operation leads to a problem that charging and discharging currents of DQ lines are increased, resulting in an increase of the power consumption of the chip.
In addition, the number of data lines has been increased in accordance with technical developments in recent years. Accordingly, the ratio of the power consumption of DQ lines to the entire power consumption of a semiconductor memory device has increased, so that the power consumption of DQ lines cannot be negligible.
Further, a conventional memory system using a semiconductor memory device as described above must use an expensive ceramic package in order to overcome heat generation caused by an increase of the power consumption, so that the cost of the entire system is increased.